I'm a final year electronics undergraduate student and I do have great interest in Digital VLSI, FPGA prototyping, RTL Design and verification. In my undergrad I have tinkered a lot with FPGAs, Microcontrollers and circuit designs. I have made my small RISC-V core in verilog. Also made a 8 bit computer using SAP (Simple as possible!) Logic and simulated it in Logisim.
I'm a former verification Research Intern at SHAKTI , RISE LAB, IITM. SHAKTI is an open-source initiative by RISE group at IIT-Madras with the aim to produce production grade processors, complete System on Chips (SoCs), development boards and SHAKTI-based software platform.
I was selected in Google Summer of Code 2021 (GSOC'21) with beagleboard org. I had worked on a FPGA cape named BeagleWire and developed Gateware for it.
I'm always open to Research opportunities in Computer Architecture, RTL Design, Verification and FPGA prototyping.

Check my resume for more details: [RESUME]
Contact me on oabhilare_b19@el.vjti.ac.in

Education

Veermata Jijabai Technological Institute, Mumbai, India.
B.Tech in Electronics Engineering (CGPA: 9.02/10) (2018-2022)

• Relavant Coursework : Electronics Circuit Analysis and Design, Digital Combinational Circuits, Digital Sequential Circuits, Microprocessor and Microcontroller, Principle of VLSI, Embedded Systems

Skills

• FPGAs : Xilinx’s Arty A7-100, KV260, Zynq ZC702, Altera’s Cyclone II, Lattice’s ICE40UP5K & iCE40HX4k, Anlogic’s EG4S20
• Langugaes : Verilog, VHDL, C, Python, Assembly Language(x86, RISC-V).
• EDA Tools : Quartus Prime, Xilinx Vivado, IceStorm.
• Microcontrollers : ESP32, ESP8266, Atmega328p, AM335x.
• Software & Frameworks : CoCotb, Icarus Verilog, GTKWave, Autodesk Eagle, Altium, Kicad, Proteus, Multisim, Logisim, Git, Linux.

Experience

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