I'm a final year electronics undergraduate student and I do have great interest in Digital VLSI, FPGA prototyping, RTL Design and verification. In my undergrad I have tinkered a lot with FPGAs, Microcontrollers and circuit designs. I have made my small RISC-V core in verilog. Also made a 8 bit computer using SAP (Simple as possible!) Logic and simulated it in Logisim.
I'm a former verification Research Intern at SHAKTI , RISE LAB, IITM. SHAKTI is an open-source initiative by RISE group at IIT-Madras with the aim to produce production grade processors, complete System on Chips (SoCs), development boards and SHAKTI-based software platform.
I was selected in Google Summer of Code 2021 (GSOC'21) with beagleboard org. I had worked on a FPGA cape named BeagleWire and developed Gateware for it.
I'm always open to Research opportunities in Computer Architecture, RTL Design, Verification and FPGA prototyping.

Check my resume for more details: [RESUME]
Contact me on oabhilare_b19@el.vjti.ac.in

Education

Veermata Jijabai Technological Institute, Mumbai, India.
B.Tech in Electronics Engineering (CGPA: 9.02/10) (2018-2022)

Relavant Coursework : Electronics Circuit Analysis and Design, Digital Combinational Circuits, Digital Sequential Circuits, Microprocessor and Microcontroller, Principle of VLSI, Embedded Systems

Experience

SHAKTI, RISE LAB, IITM

Verification Research Intern

March 2021 - August 2021

Designed and developed an FPGA framework to verify the SHAKTI processors on the FPGAs.
Developed a Python Wrapper called AAPG on FPGA which automatically generates single and multiple aapg tests which are suitable to run on the FPGA. These tests are random RISC-V programs to verify RISC-V cores.
OpenOCD and GDB are used for flashing the test program to the Arty A7-100 FPGA which is running a soft-core Vajra SOC. The python wrapper also compares the FPGA’s test signature dump with the reference software spike signature dump.
Proposed work increased the verification speed while maintaining visibility and control in the FPGA flow.
Studied and tested a cocotb UVM Framework for the verification of SSPI and MBOX IPs of SHAKTI
[REPORT] | [Completion Letter]

BeagleBoard @ Google Summer of Code 2021

Open Source Developer

June 2021- August 2021

Built and tested a Gateware for Beaglewire(Lattice iCE40 FPGA-cape) for Beaglebone Black.
Interfaced AM335x Arm Chip with Lattice FPGA using protocols like GPMC and Wishbone.
Designed and verified GPMC to Wishbone converter IP. It supported single read and writes, also included two flop synchronizer to ensure synchronization.
Developed wishbone slave examples for Beaglewire. Designed 1 Master to N slaves Wishbone Intercon for Beaglewire which were used to test multiple slave condition.
Interfaced BeagleWire with SDRAM using litedram core which included serv a bit-serial RISC-V CPU for initialization of SDRAM IP.
Designed a VGA Driver for Beaglewire, tested the design in Hardware with VGA PMOD. Developed a gateware for PONG game and Encoder PMOD for Beaglewire.
[REPORT] | [Software Repo]

FireFly LED Products Pvt Ltd

R&D Intern

May 2019 - July 2019

Designed Metal Core Printed Circuit Boards(MCPCBs) using Altium for LED lights with an on-board driver, tested the design with driver ICs from different manufactures.
Researched and Designed an optimal combination of driver IC and LED circuit design which had maximum efficiency.

news

Oct 1, 2021	Got a Arm Cortex-M23 Based MCU for Testing Review.
Sep 15, 2021	2021 Summer Work Presentation
Aug 31, 2021	Completed GSOC'21 project with beagleboard org
Jul 30, 2021	Completed Verification Research Internship at SHAKTI, RISE LAB, IITM.